| CODE | MNE5112 | ||||||||||||
| TITLE | VLSI DSP Units | ||||||||||||
| UM LEVEL | 05 - Postgraduate Modular Diploma or Degree Course | ||||||||||||
| MQF LEVEL | 7 | ||||||||||||
| ECTS CREDITS | 5 | ||||||||||||
| DEPARTMENT | Microelectronics and Nanoelectronics | ||||||||||||
| DESCRIPTION | This unit covers helps students translate DSP concepts into hardware. The following topics will be covered: digital filters (FIR and IIR), Neural networks (including multilayer perceptron, radial basis functions, self-organising maps). The unit also covers optimization of arithmetic operations (adders, multipliers, signed arithmetic, fractions multiplier-accumulator units, parallel processing units), algorithms and architectures for digital processors including accumulators, differentiators, decimation, interpolation filters. Finally implementation techniques on FPGA platform using HDL will be covered. Study-unit Aims: The unit aims at introducing the implementation of different DSP building blocks using hardware description languages. Optimization techniques of different arithmetic units are presented. Learning Outcomes: 1. Knowledge & Understanding: By the end of the study-unit the student will be able to: 鈥� understand the basic building blocks used to implement a DSP chip and how these will interact together; 鈥� optimize hardware circuitry to meet design specifications including: high speed design, low power design and low chip areas; 鈥� be able to integrate DSP building blocks into larger DSP system units. 2. Skills: By the end of the study-unit the student will be able to: 鈥� design DSP building blocks and associated data handling techniques using HDL; 鈥� implement DSP FPGA/ASIC designs that meeting system specifications; 鈥� use IP Cores to implement DSP architectures, that are capable of compressing, analyzing and recognising signal data. Main Text/s and any supplementary readings: Ciletti, Advanced Digital Design with Verilog HDL, Prentice Hall, 0-13-089161-4 Madisetti, Vijay K, VLSI Digital Signal Processors 鈥� An Introduction to Rapid Prototyping and Design Synthesis, IEEE Press, 0-7506-9406-8 |
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| RULES/CONDITIONS | Before TAKING THIS UNIT YOU ARE ADVISED TO TAKE MNE3002 | ||||||||||||
| STUDY-UNIT TYPE | Lecture and Tutorial | ||||||||||||
| METHOD OF ASSESSMENT |
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| LECTURER/S | Edward Gatt |
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The University makes every effort to ensure that the published Courses Plans, Programmes of Study and Study-Unit information are complete and up-to-date at the time of publication. The University reserves the right to make changes in case errors are detected after publication.
The availability of optional units may be subject to timetabling constraints. Units not attracting a sufficient number of registrations may be withdrawn without notice. It should be noted that all the information in the description above applies to study-units available during the academic year 2025/6. It may be subject to change in subsequent years. |
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