Please use this identifier to cite or link to this item: /library/oar/handle/123456789/125408
Title: Data-driven background subtraction algorithm for in-camera acceleration in thermal imagery
Authors: Makantasis, Konstantinos
Nikitakis, Antonios
Doulamis, Anastasios D.
Doulamis, Nikolaos D.
Papaefstathiou, Ioannis
Keywords: Infrared imaging -- Data processing
Optical data processing
Image processing -- Digital techniques
Gaussian processes -- Data processing
Field programmable gate arrays
Issue Date: 2018
Publisher: Institute of Electrical and Electronics Engineers
Citation: Makantasis, K., Nikitakis, A., Doulamis, A. D., Doulamis, N. D., & Papaefstathiou, I. (2018). Data-driven background subtraction algorithm for in-camera acceleration in thermal imagery. IEEE Transactions on Circuits and Systems for Video Technology, 28(9), 2090-2104.
Abstract: Detection of moving objects in videos is a crucial step toward successful surveillance and monitoring applications. A key component for such tasks is called background subtraction and tries to extract regions of interest from the image background for further processing or action. For this reason, its accuracy and real-time performance are of great significance. Although effective background subtraction methods have been proposed, only a few of them take into consideration the special characteristics of thermal imagery. In this paper, we propose a background subtraction scheme, which models the thermal responses of each pixel as a mixture of Gaussians with unknown number of components. Following a Bayesian approach, our method automatically estimates the mixture structure, while simultaneously it avoids over-/underfitting. The pixel density estimate is followed by an efficient and highly accurate updating mechanism, which permits our system to be automatically adapted to dynamically changing operation conditions. We propose a reference implementation of our method in reconfigurable hardware achieving both adequate performance and low-power consumption. Adopting a high-level synthesis design and demanding floating point arithmetic operations are mapped in reconfigurable hardware, demonstrating fast prototyping and on-field customization at the same time.
URI: https://www.um.edu.mt/library/oar/handle/123456789/125408
Appears in Collections:Scholarly Works - FacICTAI

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