Energy efficient memory architectures for next-generation wearable healthcare devices

Abstract

The paper explores low-power design strategies for SRAM cells in wearable and implantable devices (WIDs) to address critical power limitations that hinder further miniaturization. FinFET solves the problem of leakage current (I_Leakage) by improving the challenging power versus performance trade-off. This research develops 7-Transistor SRAM cells based on FinFETs using the Multi Threshold CMOS (MTCMOS) and Upper Self Controllable Voltage Level (USVL) methods. Using 45 nm FinFET technologies, the design and simulation of all design circuits are carried out with Cadence Virtuoso. The work adopts a multi-disciplinary approach, combining device-circuit co-design to achieve ultra-low-power operations suitable for complex tasks in wearable and implantable micro systems. The proposed design shows that the USVL method of a 7T SRAM using FinFET is more effective than the MTCMOS methodology in terms of leakage power and leakage currents. Additionally, among other proposed approaches, a comparative analysis of leakage currents and leakage power is conducted. Key outcomes include significant improvements in leakage power through FinFET-based SRAM cell using USVL technique. This paper contributes to advancing low-leakage wearable/ implantable devices (WIDs) by integrating innovative leakage reduction techniques with cutting-edge low-power circuit designs. The proposed design achieves a minimum leakage current of 10.6 nA and leakage power of 26.98nW by utilizing USVL approach. Compared to SRAM cells designed with the MTCMOS technique, the proposed method results in approximately 17.8% and 28% reduction in leakage power and leakage current, respectively. The findings pave the way for developing smaller, smarter, and sustainable wearable and implantable devices capable of complex tasks without reliance on batteries.