Warpage issues in large area mould embedding technologies

Abstract

The need for higher communications speed, heterogeneous integration and further miniaturisation have increased demand in developing new 3D integrated packaging technologies which include wafer-level moulding and chip-to-wafer interconnections . Wafer-level moulding refers to the embedding of multiple chips or heterogeneous systems on the wafer scale. This can be achieved through a relatively new technology consisting of thermal compression moulding of granular or liquid epoxy moulding compounds. Experimental measurements from compression moulding on 8鈥� blank wafers have shown an unexpected tendency to warp into a cylindrical-shape following cooling from the moulding temperature to room temperature. Wafer warpage occurs primarily as a result of a mismatch between the coefficient of thermal expansion of the resin compound and the Si wafer. This paper will delve into possible causes of such asymmetric warpage related to mould, dimensional and material characteristics using finite element (FE) software (ANSYS Mechanical). The FE model of the resin on wafer deposition will be validated against the measurement results and will be used to deduce appropriate guidelines for low warpage wafer encapsulation.